A Cost-efficient and High-performing FPGA Design and Implementation of a MIMO-OFDM Transceiver for Video Communication.

Abstract

Multiple Input Multiple Output (MIMO)-Orthogonal Frequency Division Multiplexing (OFDM) involves the transmission of modulated data in multiple spatial streams where each stream consists of multiple orthogonal subcarriers. However, we have observed that existing hardware implementations of MIMO-OFDM systems incur high hardware resources and are less suitable for implementation, especially in low-power embedded systems. In order to address this research gap, we designed and implemented a low-cost MIMO-OFDM system suitable for video transmission in a Field Programmable Gate Array (FPGA), still maintaining high performance requirements demanded by video communication. Specifically, a system with programmable pilot sequences and a modulation technique consisting of an inter- and intra-pixel interleaver and a 3-stage BCH code was designed that can correct up to 5 bits per pixel. A precomputed Lookup Table (LUT) and a simplified third-order generator polynomial were used to reduce the complexity of the error correction code. Synchronization was done at the receiver with LUT-based square root approximation, shift register-based correlators, and Karatsuba-like multiplications with fixed-point arithmetic. The hardware complexity was further reduced by time division multiplexing among the four streams and pipelining was used within OFDM stages. The channel matrix was estimated using the least squares method and adaptive channel equalization was performed with mitigated noise amplification by computing the infinity norm of the difference between the last known channel matrix and the present channel matrix to decide whether to proceed with singular value decomposition for computing the inverse of the channel matrix. Finally, the system was implemented on Artix 7 FPGAs and verified using extensive simulations and tested for real data communication, and results showed that the proposed system is power efficient (< 20 W), has high throughput (around 70 Mbps for QPSK), has low cost (< 20000 LUTs and flip-flop), and has low latency (< 1000 μs) compared to existing techniques.